Memory controller, semiconductor integrated circuit device, microcomputer, and electronic equipment

ABSTRACT

An auto refresh control circuit of a memory controller comprises an auto refresh request generation circuit that generates auto refresh requests at the predetermined intervals, a hold count circuit that holds an auto refresh request to the dynamic random access memory in the state of being impossible to access a memory for auto-refreshing at the timing of generation of the auto refresh request and counts a number of holds, and a circuit that executes a held auto refresh request to the dynamic random access memory until the number of times of executing reaches the number of holds, when detecting the idle state. When the held auto refresh request is executed, the number of holds is updated based on the number of times the held auto refresh request is executed.

RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No.2004-124388 filed Apr. 20, 2004 which is hereby expressly incorporatedby reference herein in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a memory controller, a semiconductorintegrated circuit device, a microcomputer, and electronic equipment.

2. Related Art

When refreshing is executed for a SDRAM, either a method of waitinguntil the so called idle state, in which there is no read/write accessto the SDRAM, or a method of interrupting a read/write access isadopted.

In the method of waiting until the idle state, there is a problem thatif a new refresh request is generated in the state of waiting forrefreshing of the SDRAM, the previous refresh request is cancelled and,as a result, refreshing is not executed the number of times specifiedfor the SDRAM.

On the other hand, in the method of interrupting read/write from/to theSDRAM, there is a problem that a continuous access to the SDRAM is notsecured in performing a critical process for the SDRAM.

The present invention addresses the above problems and is intended toprovide a memory controller, a semiconductor integrated circuit device,a microcomputer, and electronic equipment that do not allow refreshingto be executed an insufficient number of times and can secure read/writefrom/to the SDRAM in performing a critical process.

SUMMARY

The present invention is a memory controller, comprising an auto refreshcontrol circuit that executes an auto refresh control on a dynamicrandom access memory, the auto refresh control circuit comprising: anauto refresh request generation circuit that generates an auto refreshrequest at a predetermined interval; a hold count circuit that holds anauto refresh request to the dynamic random access memory in a state ofbeing impossible to access a memory for auto-refreshing at the timing ofgeneration of the auto refresh request and counts a number of holds; anda circuit that executes a held auto refresh request to the dynamicrandom access memory until the number of times of executing reaches thenumber of holds, when a state becomes an idle state; when the held autorefresh request is executed, the hold count circuit updating the numberof holds based on a number of times the held auto refresh request isexecuted.

The dynamic random access memory includes a DRAM and a synchronous DRAM(hereinafter, referred to as a SDRAM).

The SDRAM is a DRAM that is characterized in that an execution ofread/write is synchronized with a clock. Operations of read/writefrom/to the DRAM and SDRAM are carried out by inputting commands.

The DRAM and SDRAM have, as their main states, the idle state, which isthe state of waiting for input of a command from a host, the memoryread/write state such as the read state, in which a command and anaddress are input and the data with an address subsequent to the inputaddress is output to the host, and the write state, in which the inputdata is written at the address subsequent to the input address, and theauto refresh state, in which refreshing is executed at predeterminedintervals.

In this case, a predetermined interval is, for example, 16 microseconds.

The auto refresh request generation circuit may measure a predeterminedinterval by using a counter (auto refresh interval measurement counter)or the like to generate pulses or the like for an auto refresh requestat predetermined intervals.

If the dynamic random access memory is in the idle state at the timingof an auto refresh request, the auto refresh request can be executed tothe dynamic random access memory.

In the present invention, generated auto refresh requests are heldduring memory read/write, and the number of held auto refresh requestsis recorded, for example, in an auto refresh hold counter. At the pointwhen the memory read/write request is completed and the state becomesthe idle state, whether there are one or more holds of auto refreshrequests is checked, and if the presence of one or more holds is found,auto-refreshing is executed the number of times corresponding to theholds.

The DRAM (dynamic access memory), as its characteristics, need executerefreshing the specified number of times within a given period. If thisauto-refreshing is not executed, data stored in a memory is not secured,and may be lost.

In the conventional method of waiting until the idle state and executingan auto refresh request, there is a problem that if a new refreshrequest is generated in the state of waiting for refreshing, theprevious refresh request is cancelled and refreshing is therefore notexecuted the number of times specified for the dynamic random accessmemory. According to the present invention, however, the numbernecessary for refreshing can be kept until refreshing is executed.

Refreshing the necessary number of times in the idle state do not allowrefreshing to be executed an insufficient number of times and can secureread/write from/to the DRAM in performing a critical process.

In the memory controller of the present invention, the auto refreshcontrol circuit comprising: a forced refresh execution timing detectioncircuit that compares the number of holds to a predetermined thresholdset for forced-refreshing and detects forced refresh execution timing;and a forced auto refresh execution circuit that interrupts the state ofbeing impossible to access the dynamic random access memory when forcedrefresh execution timing is generated and executes a held auto refreshrequest.

The forced refresh execution timing is, for example, the time at whichthe value of an auto refresh hold counter for counting the number ofholds of auto refresh requests exceeds the threshold, or becomes morethan the value of the threshold.

Upon detecting forced refresh execution timing, the forced refreshexecution timing detection circuit may output, for example, forcedrefresh request signals (for example, making forced refresh requestsignals at H level).

The state of being impossible to access a dynamic random access memorymeans, for example, a break of memory access for read/write or the likein the case where access to the dynamic random access memory forread/write or the like is impossible.

When the forced refresh execution timing is generated, the forced autorefresh execution circuit interrupts an access request or the likecurrently during execution, which causes an obstruction to an autorefresh request, and forcibly executes the auto refresh request.

For example, in the case where a large number of masters alternatelyaccess a memory controller, it can be supposed that the state does notreturn to the idle state and memory read/write is continuouslygenerated.

According to the present invention, however, if the number of holdsexceeds a predetermined threshold set for a forced refresh,auto-refreshing has a priority even during the memory read/write(refreshing is forcibly executed). Namely, refreshing is forciblyexecuted in the case where auto-refreshing is inevitably necessary; theloss of data stored in the memory can thereby be avoided.

In the memory controller of the present invention, when an accessrequest is generated during execution of two or more held auto refreshrequests, the auto refresh control circuit interrupts a continuous autorefresh request.

In the present invention, when an access request is generated duringexecution of two or more continuous auto-refreshing, the auto-refreshingcan be immediately interrupted to give priority to the access request.

Accordingly, when an access request is generated during execution of aplurality of held auto-refreshing, the delay in access can be prevented.

In the memory controller of the present invention, when accessresponding to the generated access request finishes and the statebecomes the idle state, the auto refresh control circuit executes a heldauto refresh request that has still not been executed due tointerruption of a continuous auto refresh request.

According to the present invention, the auto refresh that is notexecuted (is held) due to interruption is executed at the point when thememory read/write request is completed and the memory controller becomesidle again.

The present invention is a semiconductor integrated circuit devicecomprising the memory controller according to any one of the above.

The present invention is a microcomputer comprising the memorycontroller according to any one of the above.

The present invention is electronic equipment comprising themicrocomputer according to the above, an input means of data to beprocessed by the microcomputer, and an LCD output means for outputtingdata processed by the microcomputer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining a semiconductor integrated circuitdevice of the present embodiment.

FIG. 2 is a timing chart for explaining features of the presentembodiment.

FIG. 3 is a diagram for explaining a first auto refresh control of thepresent embodiment.

FIG. 4 is a diagram for explaining a second auto refresh control of thepresent embodiment.

FIG. 5 is a diagram for explaining a third auto refresh control of thepresent embodiment.

FIG. 6 is an example of a hardware block diagram of a microcomputer ofthe present embodiment.

FIG. 7 is an example of a block diagram of electronic equipment of thepresent embodiment.

FIGS. 8A, 8B, and 8C are examples of outline views of variety types ofelectronic equipment.

DETAILED DESCRIPTION

Memory Controller, Semiconductor Integrated Circuit Device

A preferred embodiment of the present invention will be described indetail below with reference to the drawings.

FIG. 1 is a diagram for explaining a memory controller and asemiconductor integrated circuit device of the present embodiment.

A memory controller 110 of the present embodiment comprises a memorycontroller 110 that outputs signals 170, 172, 174, 176, and 178 tocontrol access to a SDRAM 200 based on access requests 160 and 162 froma host (CPU or DMA).

A semiconductor integrated circuit device 100 of the present embodimentincludes the memory controller 110 of the present embodiment.

The memory controller 110 is connected to a host (CPU or DMA) 10 and theSDRAM 200, and includes an auto refresh control circuit 190 and anaccess request generation circuit 180.

The auto refresh control circuit 190 includes an auto refresh requestgeneration circuit 120, a hold count circuit 130, a forced refreshexecution timing detection circuit 140, a forced refresh executioncircuit 150, a continuous refresh execution circuit 160, and a statemachine 170.

The auto refresh request generation circuit 120, which includes an autorefresh interval measurement counter 122, measures a predeterminedinterval by using the auto refresh interval measurement counter 122 andgenerates auto refresh requests at predetermined intervals.

The hold count circuit 130 includes an auto refresh hold counter 132.When the state is not in the idle state at the timing of generating anauto refresh request, the auto refresh request to the dynamic randomaccess memory is held and the auto refresh hold counter 132 counts andkeeps the number of times the auto refresh request is held. When theheld auto refresh request is executed, the number of holds is updatedbased on the number of times the held auto refresh request is executed.

When detecting the idle state, the continuous refresh execution circuit160 executes a held auto refresh request to the dynamic random accessmemory until the number of times of executing reaches the number ofholds.

The forced refresh execution timing detection circuit 140 compares thenumber of holds to a predetermined threshold that is set forforced-refreshing, and detects the forced refresh execution timing.

When the forced refresh execution timing is generated, the forcedrefresh execution circuit 150 interrupts the state of being impossibleto access the dynamic random access memory, and executes the autorefresh request that has been held.

The state machine 170 is hardware that shifts its state in accordancewith an access request from the host and the state of the SDRAM 200.

The continuous refresh execution circuit 160 and the forced refreshexecution circuit 150 may interrupt a continuous auto refresh requestwhen an access request is generated during execution of two or more heldauto refresh requests.

When the access responding to the generated access request finishes andthe state becomes the idle state, the continuous refresh executioncircuit 160 may execute the held auto refresh request that has still notbeen executed due to interruption of a continuous auto refresh request.

The access request generation circuit 180 generates and outputs signals170, 172, 174, 176, and 178 to control access to the SDRAM 200 based onaccess requests 160 and 162 from a host (CPU or DMA) 10 and shift of thestate of the state machine 170.

In the SDRAM 200, for example, a large number of memory cells are placedin vertical and horizontal directions and memory elements are providedat intersections of horizontal (row) direction lines and vertical(column) direction lines. The horizontal (row) direction line is a wordline, which is selected by the row address strobe (RAS) 174. Thevertical (column) direction line is a data line, which is designated bythe column address strobe (CAS) 176. The write enable signals (WEsignals) 178 are designation signals in writing the data (SDATA) 172,which is output from the memory controller 110, to the SDRAM 200,whereby the data is written at the address selected by the RAS 174 andCAS 176. Incidentally, the SDRAM 200 comprises, for example, a pluralityof memories and a memory is selected by chip select signals (CS signals)180.

The memory controller 110 creates the RAS 174 and CAS 176 according toaddress signals (Address) 160 supplied from the host (CPU or DMA) 10.The memory controller 110 also writes data (Data) 162 output from thehost (CPU or DMA) 10 at the address designated by the RAS or CAS.

For example, when a read access request is output from the host (CPU orDMA) 10, the memory controller 110 prepares for data reading (readprocessing) according to the address signals (Address) 160. The memorycontroller 110 outputs the RAS 174 in synchronization with the CSsignals 176 (activating the RAS), and subsequently outputs the CAS 176to read the data from the corresponding address of the SDRAM 200. Thenthe memory controller 110 outputs the RAS 174 and WE signals 178 toperform precharge.

When a write access request is output from the host (CPU or DMA) 10, asthe above, the memory controller 110 prepares for data writing (writeprocessing), outputs the RAS 174 in synchronization with the CS signals180 (activating the RAS), and subsequently outputs the CAS 176 and WEsignals 178 to read the data from the corresponding address of the SDRAM200. Then, as the above, the memory controller 110 outputs the RAS andWE signals 178 to perform precharge.

FIG. 2 is a timing chart for explaining features of the presentembodiment.

The case in which an auto refresh request is held a plurality of timesand then auto-refreshing is forcibly executed will be described.

210 indicates auto refresh request generation timing, and auto refreshrequests 212,214, and 216 are generated at predetermined intervals.

220 indicates the number of times of auto refresh holds that is kept bythe auto refresh hold counter. The number is incremented for each holdof a generated auto refresh request, and is decremented for eachexecution of a held auto refresh request.

230 indicates forced refresh signals showing that the set value of aforced refresh (a predetermined threshold set for a forced refresh,which is set to be six in this case) is exceeded. When the number oftimes of auto refresh holds 220 kept by the auto refresh hold counterexceeds the set value of forced-refreshing, the forced refresh signalschange from a first level (for example, L level) to a second level (forexample, H level).

240 indicates the state of the memory interface.

When an auto refresh request is generated at the timing of 212, thememory controller is in the read/write (R/W) state (241); the autorefresh request is held and the number of times of auto refresh hold 220increments from 5 to 6 (refer to 222).

This means that the number of times of auto refresh holds 220 exceedsthe set value of a forced refresh, 6, and the forced refresh signalschange from the first level (for example, L level) to the second level(for example, H level) (refer to 232).

By changing the forced refresh signals to the second level (for example,H level), the R/W request (241) is interrupted, and after the state oncebecomes the idle state (242), auto-refreshing begins (243).

At this point, auto-refreshing for six times that has been held isexecuted; the value of the auto refresh hold counter is decremented asone auto-refreshing is completed (refer to 224).

The forced refresh signals that once became the second level (forexample, H level) change to the first level (for example, L level)(refer to 234).

For example, in the case of an access request being generated duringexecution of two or more held auto refresh requests, if a continuousauto refresh request is interrupted and the access request correspondingto the generated access request is executed, the forced refresh signalsmay be left as being at the second level (H level) Thus, when the accesscorresponding to the generated access request is completed and the statebecomes the idle state, reference to the forced refresh signals is made,and if the forced refresh signals are at the second level (H level), aheld auto refresh request is executed again. As a result, the held autorefresh request, which has still not been executed due to interruptionof a continuous auto refresh request, can be completed.

When an auto refresh request is generated at the timing of 214, thememory controller is in the R/W state (244); the auto refresh request isheld and the number of times of auto refresh hold 220 increments from 0to 1 (refer to 227).

When the R/W (244) is completed and the state returns to the idle state(245), a held auto refresh request (246) is executed to the dynamicrandom access memory until the number of times of execution reaches thenumber of holds, resulting in decrement of the number of holds (refer to228).

FIG. 3 is a diagram for explaining a first auto refresh control of thepresent embodiment.

In the first auto refresh control, a refresh request is held until thememory access becomes the idle state.

After the memory controller initializes the SDRAM, the SDRAM can be inthree states, the idle state, the auto refresh state, and the read/writestate.

In the present embodiment, a state machine of the memory controllerstores the above states of the SDRAM as three states, idle (ST1), autorefresh (ST3), and memory read/write (ST2).

The timing of auto-refreshing is counted by the auto refresh intervalmeasurement counter; a request of auto-refreshing is generated in aspecific cycle. The memory controller holds auto-refreshing duringmemory read/write and records the number of holds of auto-refreshing inthe auto refresh hold counter 132.

In the idle (ST1) state of the state machine, when a memory read/writerequest (a1) from the CPU is generated, read/write is requested to theSDRAM and the state of the state machine shifts to the memory read/write(ST2).

When completion of a memory read/write request (a2) is detected, thestate of the state machine shifts to the idle (ST1).

In the idle (ST1) of the state machine, when there are one or more autorefresh requests (for example, the value of the auto refresh holdcounter is one or more) (a3), the state of the state machine shifts tothe auto refresh (ST3) and auto-refreshing is executed the number oftimes of holds, which is kept in the auto refresh hold counter.

When completion of an auto refresh request of the SDRAM (a4) isdetected, the state of the state machine shifts to the idle (ST1).

Thus in the present embodiment, the generated auto refresh request isheld until the memory read/write request is completed and the statebecomes the idle (ST1), whether there are one or more auto refreshrequests is checked at the point when the state becomes the idle (ST1),and if the presence of one or more auto refresh requests is found, thestate shifts to the auto refresh (ST3). Auto-refreshing is executed thenumber of times of holds, which is kept in the auto refresh holdcounter, and then the state returns to the idle (ST1).

According to the present embodiment, there is therefore no interruptioncaused by refreshing during continuous access. The number of necessaryrefreshing can be kept until refreshing is executed.

FIG. 4 is a diagram for explaining a second auto refresh control of thepresent embodiment.

In the second auto refresh control, a refresh request is held until thememory becomes the idle state, and when a memory read/write request isgenerated during execution of auto-refreshing, the auto-refreshing isimmediately interrupted to give priority to the read/write of thememory.

After the memory controller initializes the SDRAM, the SDRAM can be inthree states, the idle state, the auto refresh state, and the read/writestate.

In the present embodiment, the state machine of the memory controllerstores the above states of the SDRAM as three states, idle (ST1), autorefresh (ST3), and memory read/write (ST2).

The timing of auto-refreshing is counted by the auto refresh intervalmeasurement counter; a request of auto-refreshing is generated in aspecific cycle. The memory controller holds auto-refreshing duringmemory read/write and records the number of holds of auto-refreshing inthe auto refresh hold counter 132.

In the idle (ST1) state of the state machine, when a memory read/writerequest (b1) from the CPU is generated, the read/write is requested tothe SDRAM and the state of the state machine shifts to the memoryread/write (ST2).

When completion of a memory read/write request (b2) is detected, thestate of the state machine shifts to the idle (ST1).

In the idle (ST1) state of the state machine, when there are one or moreauto refresh requests (for example, the value of the auto refresh holdcounter is one or more) (b3), the state of the state machine shifts tothe auto refresh (ST3) and auto-refreshing is executed the number oftimes of holds recorded in the auto refresh hold counter.

When a memory read/write request is generated during execution ofauto-refreshing, the auto refresh is immediately interrupted, the stateof the state machine shifts to the idle (ST1) to give priority to theread/write of the memory, read/write is requested to the SDRAM, and thestate of the state machine shifts to the memory read/write (ST2).

When completion of an auto refresh request of the SDRAM (b4) is detectedwithout generation of memory read/write request from the CPU duringauto-refreshing, the state of the state machine shifts to the idle(ST1).

Thus in the present embodiment, the generated auto refresh request isheld until the memory read/write request is completed and the statebecomes the idle (ST1), whether there are one or more auto refreshrequests is checked at the point when the state becomes the idle (ST1),and if the presence of one or more auto refresh requests is found, thestate moves to the auto refresh (ST3). Refreshing is then executed thenumber of times of holds of auto-refreshing, which is kept in the autorefresh hold counter.

If memory read/write is generated during this period, however, theauto-refreshing is interrupted immediately to give priority to thememory read/write.

As a result, when an access request is generated from the CPU duringexecution of a plurality of auto-refreshing, the delay in processing canbe prevented.

FIG. 5 is a diagram for explaining a third auto refresh control of thepresent embodiment.

In the third auto refresh control, a refresh request is held until thememory becomes the idle state, and when a memory read/write request isgenerated during execution of auto-refreshing, the auto-refreshing isimmediately interrupted to give priority to the read/write of thememory. Even during the read/write of the memory, however, if the numberof holds of auto-refreshing exceeds the set value, auto-refreshing isforcibly executed.

After the memory controller initializes the SDRAM, the SDRAM can be inthree states, the idle state, the auto refresh state, and the read/writestate.

In the present embodiment, the state machine of the memory controllerstores the above states of the SDRAM as three states, idle (ST1), autorefresh (ST3), and memory read/write (ST2).

The timing of auto-refreshing is counted by the auto refresh intervalmeasurement counter; a request of auto-refreshing is generated in aspecific cycle. The memory controller holds auto-refreshing duringmemory read/write and records the number of holds of auto-refreshing inthe auto refresh hold counter 132.

In the idle (ST1) state of the state machine, when a memory read/writerequest (c1) from the CPU is generated, the read/write is requested tothe SDRAM and the state of the state machine shifts to the memoryread/write (ST2).

When completion of a memory read/write request (c3) is detected, thestate of the state machine shifts to the idle (ST1).

When the number of holds exceeding threshold (a predetermined set value)of the auto refresh hold counter is detected during read/write of thememory (c2), the state also shifts to the idle (ST1), and further to theauto refresh (ST3).

In the idle (ST1) state of the state machine, when there are one or moreauto refresh requests (for example, the value of the auto refresh holdcounter is one or more) (c4), the state of the state machine shifts tothe auto refresh (ST3) and auto-refreshing is executed the number oftimes of holds of auto-refreshing, which is kept in the auto refreshhold counter.

When a memory read/write request (c5) is generated duringauto-refreshing, the auto-refreshing is immediately interrupted, thestate of the state machine shifts to the idle (ST1) to give priority tothe read/write of the memory, the read/write is requested to the SDRAM,and the state of the state machine shifts to the memory read/write(ST2).

When completion of an auto refresh request of the SDRAM (c6) is detectedwithout generation of a memory read/write request (c5) from the CPUduring auto-refreshing, the state of the state machine shifts to theidle (ST1).

Thus in the present embodiment, the generated auto refresh request isheld until the memory read/write request is completed and the statebecomes the idle (ST1), whether there are one or more auto refreshrequests is checked at the point when the state becomes the idle (ST1),and if the presence of one or more auto refresh requests is found, thestate shifts to the auto refresh (ST3). Refreshing is then executed thenumber of times of holds of auto-refreshing, which is kept in the autorefresh hold counter.

If memory read/write is generated during this period, however, the autorefresh is interrupted immediately to give priority to the memoryread/write.

As a result, when an access request is generated from the CPU duringexecution of a plurality of auto-refreshing, the delay in processing canbe prevented.

Even during the read/write of the memory, if the number of holds ofauto-refreshing exceeds the set value, auto-refreshing is forciblyexecuted.

A dynamic memory, as its characteristics, need execute refreshing thespecified number of times within “a given period”. If thisauto-refreshing is not executed, data stored in the memory is notsecured, and may therefore be lost. For example, in the case where alarge number of masters alternately access a memory controller, it canbe supposed that the state does not return to the idle state and memoryread/write is continuously generated.

Even in such a case, auto-refreshing is forcibly executed in the presentembodiment if the number of holds of auto-refreshing exceeds the setvalue. As a result, data stored in the memory can be secured.

Microcomputer

FIG. 6 is an example of a hardware block diagram of a microcomputer ofthe present embodiment.

This microcomputer 700 includes a CPU 510, a cache memory 520, an LCDcontroller 530, a reset circuit 540, a programmable timer 550, a realtime clock (RTC) 660, a DRAM controllercum bus I/F 670, an interruptcontroller 580, a serial interface 590, a bus controller 600, an A/Dconverter 610, a D/A converter 620, an input port 630, an output port640, an I/O port 650, a clock generator 560, a prescaler 570, an MMU730, an image process circuit 740, and a general purpose bus 680, aspecial purpose bus 730, and various types of pins 690 that connectthese units, etc.

The RAM 720 includes a dynamic random access memory (DRAM or SDRAM)having a self-refresh function and a memory controller 722 of thepresent invention.

The memory controller 722 has, for example, a construction explained inFIG. 1.

Electronic Equipment

An example of a block diagram of electronic equipment of the presentembodiment is shown in FIG. 7. This electronic equipment 800 includes amicrocomputer (or ASIC) 810, an input unit 820, a memory 830, a powersupply generator 840, an LCD 850, and a sound output unit 860.

In this equipment, the input unit 820 is a unit for inputting varioustypes of data. The microcomputer 810 performs various types of processesbased on data that are input by this input unit 820. The memory 830becomes a work area of the microcomputer 810 or the like. The powersupply generator 840 is a unit for generating various types of powersupply used in the electronic equipment 800. The LCD 850 is a unit foroutputting various types of images Getters, icons, and graphics) thatthe electronic equipment displays.

The sound output unit 860 is a unit for outputting various types ofsound (voice, game music, or the like) and its function can beperformed: by hardware such as a speaker.

An example of an outline view of a cellular phone 950, one of electronicequipment, is shown in FIG. 8A This cellular phone 950 comprises dialbuttons 952, which function as input units, an LCD 954, which displaystelephone numbers, names, and icons, and a speaker, which functions as asound output unit to output sound.

An example of an outline view of a portable game device 960, one ofelectronic equipment is shown in FIG. 8B. This portable game device 960comprises manual operation buttons 962, which function as input units, across shape key 964, an LCD 966, which displays game images, and aspeaker 968, which functions as a sound output unit to output gamesound.

An example of an outline view of a personal computer 970, one ofelectronic equipment, is shown in FIG. 8C. This personal computer 970comprises a keyboard 972, which functions as an input unit, an LCD 974,which displays letters, numerals, and graphics, and a sound output unit976.

Incorporation of the microcomputer of the present embodiment into theelectronic equipment of FIGS. 8A to 8C can provide low-cost electronicequipment having a small memory capacity.

Incidentally, electronic equipment that can utilize the presentembodiment may be variety types of electronic equipment using an LCDsuch as a personal digital assistance, a pager, an electronic deskcalculator, a device with a touch panel, a projector, a word processor,a view finder type or monitor direct view type video tape recorder, anda car navigation device other than the electronic equipment shown inFIGS. 8A, 8B, and 8C.

Incidentally, the present invention is not restricted to the presentembodiment, but various modifications may be made in the scope of thepresent invention concepts.

1. A memory controller, comprising: an auto refresh control circuit thatexecutes an auto refresh control on a dynamic random access memory, theauto refresh control circuit including: an auto refresh requestgeneration circuit that generates an auto refresh request at apredetermined interval; a hold count circuit that holds an auto refreshrequest to the dynamic random access memory in a state of beingimpossible to access a memory for auto-refreshing at timing ofgeneration of the auto refresh request and counts holds; and a circuitthat executes a held auto refresh request to the dynamic random accessmemory until the number of times of executing reaches the number ofholds, when a state becomes an idle state, wherein when the held autorefresh request is executed, the hold count circuit updates the numberof holds based on a number of times the held auto refresh request isexecuted.
 2. The memory controller according to claim 1, wherein theauto refresh control circuit further comprises: a forced refreshexecution timing detection circuit that compares the number of holds toa predetermined threshold set for a forced refresh and detects forcedrefresh execution timing; and a forced auto refresh execution circuitthat interrupts a state of being impossible to access the dynamic randomaccess memory and executes a held auto refresh request when forcedrefresh execution timing is generated.
 3. The memory controlleraccording to claim 1, wherein when an access request is generated duringexecution of two or more held auto refresh requests, the auto refreshcontrol circuit interrupts a continuous auto refresh request.
 4. Thememory controller according to claim 3, wherein when access respondingto the generated access request finishes and a state becomes an idlestate, the auto refresh control circuit executes a held auto refreshrequest that has still not been executed due to interruption of acontinuous auto refresh request.
 5. A semiconductor integrated circuitdevice, comprising the memory controller according to claim
 1. 6. Amicrocomputer, comprising the memory controller according to claim
 1. 7.Electronic equipment, comprising: the microcomputer according to claim6; an input means of data to be processed by the microcomputer; and anLCD output means for outputting data processed by the microcomputer.